Many applications in digital signal processing require the use of complicated circuits for performing complex arithmetic calculations in real time. For example, in order to cancel echoes that occur as a result of hybrid coupling within a telephone network, adaptive Finite Impulse Response (FIR) filters have been used. Such FIR filters typically include complicated arithmetic circuits for performing reciprocal calculations, and complicated μ-Law/A-Law expander circuits for expanding μ-Law/A-Law encoded signals.
PLDs are the devices of choice in implementing these complicated digital signal processors. For many PLDs, the basic building blocks are the Logic Elements (LEs) or Logic Array Blocks (LABs) that include logic circuits that may be programmed to perform specific logic operations. Due to their complexity, digital signal processors typically require the use of many LEs. Each PLD has a limited number of LEs. Therefore, after these arithmetic circuits are implemented, few LEs are left for performing other functions. As a result, it is often difficult to implement an entire digital signal processing system with complicated arithmetic circuits on a single PLD.
Accordingly, it would be desirable to provide improved techniques for efficiently implementing complex arithmetic circuits in programmable logic devices.